1. Field of the Invention
The present invention relates generally to a fin diode structure and a method of manufacturing the same, and more particularly, to a fin diode structure with globally-doped regions in the substrate which is compatible with the process flow of normal fin field effect transistors (FinFET).
2. Description of the Prior Art
The use of fin field effect transistors (FinFETs) in the semiconductor technology keeps rising as the size of technology decreases. FinFETs are advantageous in smaller technologies because of their relatively higher drive current when compared to devices of similar size and because of their general ability to prevent short-channel effects. FinFETs generally have increased drive currents because the gate wraps around the channel such that the effective width of the channel is increased. The increased channel width allows for a greater drive current. Furthermore, by having the gate wrap around the channel, the gate can suppress leakage current through the channel more easily, thereby decreasing the short channel effects.
The above-identified advantages of FinFETs have led to their use in smaller technologies, particularly in 32 nm node and smaller. However, the trade-off for smaller size results an increased susceptibility of failure of the FinFET devices due to the electrostatic discharge (ESD) issue. It is well known in the semiconductor field that extremely high voltages can be produced in the vicinity of an integrated circuit due to the build-up of static charges. A high potential maybe generated at an input or output buffer of the integrated circuit, which may be caused by a person touching a package pin that is in electrical contact with the input or output buffer. When the electrostatic charges are discharged, a high current is produced at the package nodes of the integrated circuit, and this issue is referred as electrostatic discharge (ESD). ESD is a serious problem for semiconductor devices since it has the potential to damaging the entire integrated circuit. Especially for the FinFET device, the active area width of a FinFET is much smaller than that of another device of corresponding technology size. The smaller width may lead to increased current density in the FinFET when the ESD event occurs, which means that the tolerable and allowable threshold current density is smaller for the FinFET device.
For example, FinFETs typically have a threshold current density of 0.1 mA/μm before device breakdown occurs as compared to approximately 2 mA/μm for planar bulk MOSFETs or approximately 1.4 mA/μm for planar SOI MOSFETs. This extremely small current density may cause the dielectric gate oxide to breakdown easily between the active area and the gate and short circuit the gate and the active area. Thus, FinFETs are generally more susceptible to device failures from electrostatic discharge issue because of their relatively small channel width, and a solution is needed to overcome this problem.